1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to isotropically etching sidewall spacers formed upon the opposed sidewall surfaces of a pair of CMOS (one NMOS and one PMOS) gate conductors to reduce the lateral thickness of each spacer. The sidewall spacers are isotropically etched after performing a source/drain implant self-aligned to the pair of sidewall spacers arranged upon the NMOS gate conductor so that they may also be used to perform an LDD implant self-aligned to the pair of sidewall spacers arranged upon the PMOS gate conductor.
2. Description of the Related Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline ("polysilicon") material over a relatively thin gate oxide. The polysilicon material is then patterned to form a gate conductor directly above a channel region of the substrate. A dopant species is implanted into the gate conductor and regions of the substrate exclusive of the channel region, thereby forming source and drain regions (i.e., junctions) adjacent to and on opposite sides of the channel region. If the dopant species used for forming the source and drain regions is n-type, then the resulting MOSFET is an NMOSFET ("n-channel") transistor device. Conversely, if the dopant species is p-type, then the resulting MOSFET is a PMOSFET ("p-channel") transistor device. Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both (CMOS) on a single substrate. While both types of devices can be formed, the devices are distinguishable based on the dopant species used.
As device dimensions continue to shrink, transistor devices become more sensitive to so-called short-channel effects ("SCE"). The distance between a source-side junction and a drain-side junction is often referred to as the physical channel length. However, after implantation and subsequent diffusion of the junctions, the actual distance between junctions becomes less than the physical channel length and is often referred to as the effective channel length ("Leff"). In VLSI designs, as the physical channel becomes small, so too must the Leff. SCE becomes a predominant problem whenever Leff drops below approximately 0.2 .mu.m.
Generally speaking, SCE impacts device operation by, inter alia, reducing device threshold voltages and increasing sub-threshold currents. As Leff becomes quite small, the depletion regions associated with the source and drain areas within the junctions may extend toward one another and substantially occupy the channel area. Henceforth, some of the channel will be partially depleted without any influence of gate voltage. As a result, less gate charge is required to invert the channel of a transistor having a short Leff. Somewhat related to threshold voltage lowering is the concept of sub-threshold current flow. Even at times when the gate voltage is below the threshold value, current between the source and drain nonetheless exists for transistors having a relatively short Leff. One method in which to control SCE is to increase the dopant concentration within the body of the device. Unfortunately, increasing dopant within the body deleteriously increases potential gradients in the device.
In addition to promoting SCE, reducing device dimensions may cause the lateral electric field in MOS devices to increase, giving rise to so-called hot carrier effects ("HCE"). HCE is a phenomena in which the kinetic energy of charged carriers (holes or electrons) within the channel region of a device is increased as the carriers are accelerated through large potential gradients. As a result of this increase in kinetic energy, the charged carriers are injected into the gate oxide wherein they may become trapped. The greatest potential gradient, often referred to as the maximum electric field ("Em") occurs near the drain during saturated operation. As a result of electron entrapment within the gate oxide, a net negative charge density forms in the gate oxide. The trapped charge can accumulate with time, resulting in a positive threshold shift in an NMOS transistor, or a negative threshold shift in a PMOS transistor.
To overcome the problems related to SCE and HCE, an alternative drain structure known as the lightly doped drain ("LDD") is commonly used. The purpose of the LDD is to absorb some of the potential into the drain and thus reduce Em. A conventional LDD structure is one in which a light concentration of dopant is self-aligned to the gate conductor followed by a heavier concentration of dopant self-aligned to the gate conductor on which a pair of sidewall spacers has been formed. The purpose of the first implant dose is to produce lightly doped sections within an active area of the substrate near the channel. The second implant dose is spaced from the channel by a distance substantially equivalent to the thickness of each sidewall spacer. The second implant dose forms heavily doped source and drain regions within the active area laterally outside the LDD areas. In this manner, the lateral thickness of each sidewall spacer dictates the length of each LDD area.
Unfortunately, lateral migration of dopant species within both the source and drain regions and the LDD areas of a PMOS transistor can offset the benefits of having those LDD areas. P-type dopant species, e.g., boron, are typically relatively small in size. As such, the p-type dopant species easily diffuse through interstitial and vacancy positions within the substrate to other sections of the substrate in response to being heated during subsequent processing steps. As a result of dopant diffusion, the source and drain regions may eventually extend completely to the gate conductor while the LDD areas may extend partially underneath the gate conductor. The lateral migration of dopant species into the channel region reduces the Leff of the transistor, and thus may lead to detrimental SCE and HCE. Thus, it may be of benefit to unconventionally displace the PMOS LDD areas away from the gate conductor to provide protection against SCE and HCE.
FIGS. 1-4 illustrate a conventional sequence of processing steps which may be used to form a CMOS circuit in which the LDD areas of a PMOS transistor are laterally offset from the sidewalls surfaces of a corresponding gate conductor. FIG. 1 depicts a partial cross-sectional view of a single crystalline silicon substrate 10 which is slightly doped with n-type dopant species. Shallow trench isolation structures 14 laterally isolate active areas 6 and 8 of substrate 10. A p-type well 12 resides within an upper portion of active area 6 between a pair of isolation structures 14. A pair of gate conductors 22 are spaced above separate active areas of substrate 10 by a gate dielectric 20. For example, three pairs of sidewall spacers 24a, 24b, and 24c may be formed laterally adjacent the opposed sidewall surfaces of each gate conductor 22. Sidewall spacers 24a and 24c are typically composed of a dielectric, i.e., silicon dioxide, which is dissimilar to the dielectric, i.e., silicon nitride, from which sidewall spacers 24b are made. As such, each of the sidewall spacers 24a, 24b, and 24c may be selectively etched without removing the adjacent spacer. As shown in FIG. 1, a masking layer 26 may be formed upon active area 6 and the sidewall spacers and the gate conductor 22 residing above active area 6. Subsequent to forming masking layer 26, a p.sup.+ source/drain implant self-aligned to the exposed lateral edges of sidewall spacers 24a is forwarded into the unmasked areas of substrate 10 to from source and drain regions 28.
After removing masking layer 26, sidewall spacers 24c are removed from sidewall spacers 24b using an etch technique which is highly selective to silicon dioxide ("oxide") relative to silicon nitride ("nitride"). Another masking layer 30 is formed upon active area 8 and the structures overlying the active area, as shown in FIG. 2. Thereafter, an n.sup.+ source/drain implant self-aligned to the exposed lateral edges of sidewall spacers 24b is performed to form source and drain regions 32 within well 12. Absent sidewall spacers 24c, source and drain regions 32 are placed such that they are closer to the adjacent gate conductor 22 than are source and drain regions 28. Subsequently, masking layer 30 is removed from active area 8, and sidewall spacers 24b are removed from sidewall spacers 24a using an etch technique which exhibits a high etch selectivity ratio of nitride to oxide. After forming a masking layer 34 upon active area 6 and the structures overlying active area 6, a p.sup.- LDD implant is performed. In this manner, LDD areas 36 are formed within active area 8 laterally aligned to the exposed lateral edges of sidewall spacers 24a, immediately adjacent to source and drain regions 28.
As shown in FIG. 4, sidewall spacers 24a and masking layer 34 may then be removed, followed by the formation of a masking layer 38 upon active area 8 and the overlying gate conductor 22. An n.sup.- LDD implant which is self-aligned to the opposed sidewall surfaces of the unmasked gate conductor 22 is forwarded into well 12 to form LDD areas 40. An NMOS transistor 42 and a PMOS transistor 44 are thusly placed upon and within substrate 10. Although source and drain regions 28 and LDD areas 36 of PMOS transistor 46 may include high-diffusing dopant species, initially placing them a spaced distance from gate conductor 22 reduces the possibility that they might migrate laterally underneath the gate conductor.
The process of forming three pairs of sidewall spacers laterally adjacent each gate conductor, sequentially removing each pair of spacers, and masking certain active areas while implanting dopants into other active areas is unfortunately very time consuming. First of all, since sidewall spacers 24a and 24c are composed of oxide while sidewall spacer 24b is composed of nitride, a separate deposition and anisotropic etch step is required for each spacer. Further, each time an implantation step is performed, one mask is removed from certain active areas while another mask is formed across other active areas. Also, since a different pair of spacers is selectively etched before each implantation step, time must be allotted for the preparation of each etch process and each implantation process. It would therefore be desirable to reduce the number of processing steps, and hence the amount of time required to form a CMOS circuit in which the junctions of the PMOS transistors are laterally spaced from adjacent gate conductors while those of the NMOS transistors are positioned immediately adjacent the gate conductors.